The candidate will work closely with an in-house cryptographic algorithm team and an external circuit design team to design and implement in-memory computing IPs, as well as verify them on FPGA. The verified designs will either be passed to back-end for tape-out or as an FPGA-based product for early customer demo.
- Writing clean, high-quality, high-performance, maintainable RTL code
- Participation in code reviews
- Implement Verilog RTL from a high-level description such as one in Matlab, Python or C
- Bachelor’s degree in Electrical Engineering or Computer Science
- Familiar with RTL simulation, timing analysis.
- Familiar with FGPA digital validation and test pattern generation using logic analyzer and/or high-speed oscilloscope, etc.
- Familiar with Xilinx FPGA process in memory.
- Familiar with Xilinx IP design and packaging.
- Familiar with at least one FPGA device.
- Familiar with Custom IP and SoC integration is a plus.
Application - Resume review and email exchange.
1st round interview - Technical review.
Work sample (optional)
2nd round interview - Technical background interview with corporate partners.
Upon successful interview process, we will make an offer to the candidate and discuss on-boarding package.